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dear customers, about the change in the name such as "oki electric industry co. ltd." and "oki" in documents to oki semiconductor co., ltd. the semiconductor business of oki electric industry co., ltd. was succeeded to oki semiconductor co., ltd. on oc tober 1, 2008. therefore, please accept that although the terms and marks of "oki electric indust ry co., ltd.", ?oki electric?, and "oki" remain in the documents, they all have been changed to "oki semiconductor co., ltd.". it is a change of the company name, the co mpany trademark, and the logo, etc. , and not a content change in documents. october 1, 2008 oki semiconductor co., ltd. 550-1 higashiasakawa-cho, hachio ji-shi, tokyo 193-8550, japan http://www.okisemi.com/en/
? semiconductor msm5839b 1/11 general description the msm5839b is a dot matrix lcd segment driver lsi which is fabricated using low power cmos metal gate technology. this lsi consists of two 20-bit shift registers, two 20-bit latches, a 40-bit level shifter and a 40-bit 4-level driver. it converts serial data, which is received from an lcd controller lsi, to parallel data and outputs lcd driving waveform to the lcd panel. expansion of display can easily be made by increasing the number of characters and character patterns. this lsi can drive a variety of lcd panels because the bias voltage, which determines the lcd driving voltage, can be optionally supplied from the external source. features ? supply voltage : 4.5 to 5.5v ? lcd driving voltage : 8 to 18v ? applicable lcd duty : 1/32 to 1/128 ? bias voltage can be supplied externally ? applicable common driver : msm5238 (32 outputs) ? package options: 56-pin plastic qfp (qfp56-p-910-0.65-k) (product name: msm5839b gs-k) 56-pin plastic qfp (qfp56-p-910-0.65-l2) (product name: msm5839b gs-l2) 56-pin plastic qfp (qfp56-p-910-0.65-2k) (product name: msm5839b gs-2k) ? semiconductor msm5839b 40-dot segment driver e2b0022-27-y2 this version: nov. 1997 previous version: mar. 1996
? semiconductor msm5839b 2/11 block diagram o 1 o 2 o 19 o 20 o 21 o 22 o 39 o 40 v dd (v 1 ) v ee (v 4 ) v 2 v 3 df di 1 cp load 40-bit 4-level driver 40-bit level shifter 20-bit latch 20-bit latch 20-bit shift register 20-bit shift register v dd v ee v dd v ss v ss do 40 do 20 di 21
? semiconductor msm5839b 3/11 pin configuration 56 55 54 53 52 51 50 49 48 47 46 45 44 43 4 3 2 1 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 39 40 41 42 38 37 36 35 34 33 32 31 30 29 o 1 di 21 do 20 v ee (v 4 ) v 2 load v dd (v 1 ) di 1 df nc nc nc o 27 o 26 o 24 o 23 o 21 *(v dd ) o 20 o 18 o 17 o 16 o 15 o 2 o 3 o 4 o 5 o 6 o 7 o 8 o 9 o 10 o 11 do 40 o 40 o 39 o 38 o 37 o 36 o 35 o 34 o 33 o 32 o 31 o 12 o 30 o 13 o 29 o 14 o 28 o 19 o 22 o 25 v ss v 3 cp nc: no connection 56-pin plastic qfp (type k) 56 55 54 53 52 51 50 49 48 47 46 45 44 43 di 21 do 20 v ee (v 4 ) v 2 load v dd (v 1 ) di 1 df nc nc nc v ss v 3 cp o 1 o 2 o 3 o 4 o 5 o 6 o 7 o 8 o 9 o 10 o 11 o 12 o 13 o 14 4 3 2 1 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 o 27 o 26 o 24 o 23 o 21 *(v dd ) o 20 o 18 o 17 o 16 o 15 o 19 o 22 o 25 39 40 41 42 38 37 36 35 34 33 32 31 30 29 do 40 o 40 o 39 o 38 o 37 o 36 o 35 o 34 o 33 o 32 o 31 o 30 o 29 o 28 nc: no connection 56-pin plastic qfp (type l) * this pin is internally connected to v dd , so connect it to the power supply or leave it open. note : the figure for type l shows the configuration viewed from the reverse side of the package. pay attention to the difference in pin arrangement. (top view)
? semiconductor msm5839b 4/11 absolute maximum ratings *1 v dd >v 2 >v 3 >v ee *2 applies when a series resistor of 47 w or more is connected as shown below. parameter symbol condition rating unit supply voltage (1) v dd * 2 *1 *1 supply voltage (2) input voltage storage temperature v dd C v ee v dd C v ee v 1 t stg t a = 25c t a = 25c t a = 25c t a = 25c C 0.3 to +6 0 to 18 0 to 18 C 0.3 to v dd +0.3 C 55 to +150 v v v v c v dd v 2 v 3 v ee msm5839b v dd Cv ee +v Cv r s 47 w = > v ss
? semiconductor msm5839b 5/11 recommended operating conditions electrical characteristics dc characteristics *1 applicable to load, cp, di 1 , di 21 , df *2 applicable to do 20 , do 40 *3 v n = v dd to v ee, v 3 = (v dd Cv ee ), v 2 = (v dd Cv ee ) *4 applicable to o 1 - o 40 parameter symbol condition range unit supply voltage (1) supply voltage (2) operating temperature v dd v dd C v ee t op 4.5 to 5.5 8 to 16 C20 to +85 v v c v dd C v ee 8 to 18 v * 2 * 1 * 1 v dd v 2 v 3 v ee msm5839b v dd Cv ee +v Cv r s 3 47 w v ss *1 v dd >v 2 >v 3 >v ee *2 applies when a series resistor of 47 w or more is connected as shown below. 2 9 7 9 parameter symbol condition unit "h" input voltage v v ih 0.8v dd min. typ. max. v dd "l" input voltage v v il v ss 0.2v dd "h" input current m a i ih 1 v i = v dd "l" input current m a i il C1 v i = 0v "h" output voltage v v oh v dd C0.4 i o =C0.4ma "l" output voltage v v ol 0.4 i o = 0.4ma on resistance k w r on 3.5 7 supply current m a i dd 100 (v dd = 5v 10%, ta = C20 to +85c) * 1 * 1 * 1 * 1 * 2 * 2 * 4 *3 v dd Cv ee = 10v v n Cv o = 0.25v connect all inputs to v dd or v ss v dd Cv ee = 18v, no load
? semiconductor msm5839b 6/11 switching characteristics cp di 1 , di 21 do 20 , do 40 load 0.8v dd t w(cp) 0.8v dd t f(cp) t w(cp) 0.2v dd t r(cp) 0.8v dd 0.2v dd 0.8v dd 0.2v dd 0.8v dd 0.8v dd 0.2v dd 0.2v dd 0.8 0.8 v dd v dd 0.2 0.2 v dd v dd t hold t setup t hold t setup 0.8v dd 0.2v dd t plh t phl t cl 0.2v dd 0.2v dd t lc t f(l) t w(l) t r(l) 0.8v dd 0.8v dd parameter symbol condition unit "h", "l" propagation delay time ns tp lh min. typ. max. 250 clock frequency f cp clock pulse width ns t w (cp) 125 load pulse width ns t w (l) 125 data setup time di ? cp t setup 50 cp ? load time ns t cl 250 tp hl ns load ? cp time t lc 0 ns t hold 50 ns cp rise/fall time ns t r (cp) 50 t f (cp) load rise/fall time m s t r (l) 1 t f (l) data hold time di ? cp duty = 50% 3.3 mhz (v dd = 5v 10%, ta = C20 to +85c, c l = 15pf)
? semiconductor msm5839b 7/11 functional description pin functional description ?di 1 the data input pin for the 20-bit shift register (from 1st to 20th bit). the display data is input to the data pin in synchronization with a clock pulse. ?cp clock pulse input pin for the two 20-bit shift registers. the data is shifted in the two 20-bit shift registers at the falling edge of the clock pulse. data setup time (t setup ) and data hold time (t hold ) are required each between di 1 , di 21 and cp. refer to the switching characteristics. ?do 20 the 20th output bit of the shift register. the data which is input from di 1 is clocked out with the delay in the number of bits of the shift register (20). a 40-bit shift register can be configured by connecting the output of this pin to di 21 pin. ?di 21 the data input pin for the 20-bit shift register (from 21st to 40th bit). connecting the do 20 pin and this pin allows the device to be used as a 40-bit shift register. ?do 40 the 40th output bit of the shift register. the data which is input from di 1 is clocked out with the delay in the number of the bits of the shift register (20). when extending the number of characters, this pin is used to cascade connect the next msm5839b. ?df alternate signal input pin for lcd driving waveform. ?v dd (v 1 ), v ss supply voltage pins. v dd should be 4.5 to 5.5v. v ss is the ground pin (v ss = 0v). ?v 2 , v 3 , v ee (v 4 ) bias supply voltage pins to drive the lcd. bias voltage is supplied from an external source. ? load the signal for latching the shift register contents is input from this pin. when load pin is set at "h", the shift register contents are transferred to the 40-bit 4-level driver. when load pin is set at "l", the last display output data (o 1 to o 40 ), which was transferred when load pin was at "h", is held.
? semiconductor msm5839b 8/11 ?o 1 to o 40 display data output pins which correspond to each data bit in the latch. one of v dd , v 2 , v 3 or v ee (v 4 ) is selected as a display driving voltage source based on the combination of latched data level and df signal. refer to the truth table below. these pins should be connected to the segment side of the lcd panel. truth table latched data df lcd driver output h hv ee (v 4 ) lv dd (v 1 ) l hv 3 lv 2
? semiconductor msm5839b 9/11 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp56-p-910-0.65-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.36 typ. mirror finish
? semiconductor msm5839b 10/11 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp56-p-910-0.65-l2 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.36 typ. spherical surface
? semiconductor msm5839b 11/11 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp56-p-910-0.65-2k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.43 typ. mirror finish

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